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DS34S102 Datasheet PDF

Maxim Integrated DS34S102

the DS34S10x devices minimizes cost, board space, and time to market.
Part No. DS34S102
Datasheet DS34S102 Download
Manufacturer
Maxim Integrated
Description Single/Dual/Quad/Octal TDM-over-Packet Chip
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DS34S102 datasheet page 1 preview

GENERAL DESCRIPTION

These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standardsbased TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. The high level of integration available with ♦ ♦ ♦ ♦ ♦ ♦

FEATURES

Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable Clock Recovery Algorithm Handle...
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