Maxim Integrated DSSHA1
The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA-1 computation required for authenticating SHA-1 devices. The DSSHA1 can compute SHA-1 message authentication codes (MACs) for use with Maxim SHA-1 devices, such as the DS1963S, DS1961S, DS28E10, DS28E02, DS2460, DS28CN01, and DS28E01-100. The device can output the 20-byte MAC result from registers required for comparison against SHA-1 slave devices.| Part No. | DSSHA1 |
|---|---|
| Datasheet | DSSHA1 Download |
| Manufacturer |  Maxim Integrated |
| Description | Memory-Mapped SHA-1 Coprocessor |
| Buy | Stock & Price |
GENERAL DESCRIPTION
When incorporated into a design, DSSHA1 also provides an offloading function, relieving a microcontroller of performing the SHA-1 computation.APPLICATIONS
Printer Cartridge Authentication Clone Prevention of Systems and PCB Designs License Management Secure Feature Control of Systems Network Appliance AuthenticationFEATURES
♦ SHA-1 Computations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz) ♦ Area Estimate is 102,256µm2 in TSMC CL018G (0.18µm Generic Process) ♦ Dedicated Hardware-Accelerated SHA-1 Engine for Generating MACs ♦ 64-Byte RAM for Message Input ♦ Five 32-Bit Registers to Read MAC Result ♦ Available in Synthesizable Verilog® ♦ Made as a Low-Level Module to be Instantiated by a Top-Level Module ♦ Includes Test Bench Typical Operating Circuit MICROPROCESSOR ASIC—TOP-LEVEL MODULE DSSHA1 MODULE DESIGN MODULE DS1WM MODULE 3.3V R DS28E01-100 Verilog is a registered trademark of Gateway Design Automation Corp. _________________________________...
