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DSSHA1 - Memory-Mapped SHA-1 Coprocessor

Description

The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA-1 computation required for authenticating SHA-1 devices.

Features

  • SHA-1 Computations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz).
  • Area Estimate is 102,256µm2 in TSMC CL018G (0.18µm Generic Process).
  • Dedicated Hardware-Accelerated SHA-1 Engine for Generating MACs.
  • 64-Byte RAM for Message Input.
  • Five 32-Bit Registers to Read MAC Result.
  • Available in Synthesizable Verilog®.
  • Made as a Low-Level Module to be Instantiated by a Top-Level Module.
  • Includes Test Bench Typical O.

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Datasheet preview – DSSHA1

Datasheet Details

Part number DSSHA1
Manufacturer Maxim Integrated
File Size 239.30 KB
Description Memory-Mapped SHA-1 Coprocessor
Datasheet download datasheet DSSHA1 Datasheet
Additional preview pages of the DSSHA1 datasheet.

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    DSSHA1 19-5870; Rev 0; 5/11 Memory-Mapped SHA-1 Coprocessor General Description The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA-1 computation required for authenticating SHA-1 devices. The DSSHA1 can compute SHA-1 message authentication codes (MACs) for use with Maxim SHA-1 devices, such as the DS1963S, DS1961S, DS28E10, DS28E02, DS2460, DS28CN01, and DS28E01-100. The device can output the 20-byte MAC result from registers required for comparison against SHA-1 slave devices. When incorporated into a design, DSSHA1 also provides an offloading function, relieving a microcontroller of performing the SHA-1 computation.
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