GENERAL DESCRIPTION
Horizontal and vertical synchronization (HSYNC/VSYNC) inputs feature level-shifting buffers to support low-voltage CMOS or standard TTL-compatible graphics controllers, meeting the VESA requirement of ±8mA. DDC, consisting of SDA_ and SCL_, is a bidirectional activelevel translating switch that reduces capacitive load. See the Pin DESCRIPTION
section. All other pins are protected to ±10kV Human Body Model (HBM). The MAX4885E is specified over the extended -40°C to +85°C temperature range, and is available in the 24-pin, 4mm x 4mm TQFN package. APPLICATIONS
Notebook Computers/Docking Stations Digital Projectors Computer Monitors Servers/Storage KVM Switches FEATURES
♦ ±15kV HBM ESD Protection on Externally Routed Terminals ♦ 1GHz Bandwidth ♦ Low 5Ω (typ) On-Resistance (R, G, B Signals) ♦ Low 6pF (typ) On-Capacitance (R, G, B Signals) ♦ Low R, G, B Skew -50ps (typ) ♦ Near Zero Power Consumption (< 2µA) ♦ Ultra-Small, 24-Pin (4mm x 4mm) TQFN Package Ordering Information PART TEMP RANGE PIN-PACKAGE MAX4885EETG+ -40°C to +85°C 24 TQFN-EP* *EP = Exposed pad. +Denotes lead-free package/RoHS-compliant package.