MAX1126 Datasheet | Maxim Integrated

19-3143; Rev 1; 3/04 KIT ATION EVALU E L B AVAILA Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs General Description Features - Four ADC Channels with Serial LVDS/SLVS Outputs - Excellent Dynamic Performance 69.9d B SNR at f IN = 5.3MHz 93.7d Bc SFDR at f IN = 5.3MHz -90d B Channel Isolation - Ultra-Low Power 135m W per Channel (Normal Operation) 1.5m W Total (Shutdown Mode) - Accepts 20% to 80% Clock Duty Cycle - Self-Aligning Data-Clock to Data-Output Interface - Fully Differential Analog Inputs - Wide ±1.4VP-P Differential Input Voltage Range - Internal/External Reference Option - Test Mode for Digital Signal Integrity - LVDS Outputs Support Up to 30in FR-4 Backplane Connections - Small, 68-Pin QFN with Exposed Paddle - Evaluation Kit Available (MAX1127EVKIT) The MAX1126 quad, 12-bit analog-to-digital converter (ADC) Features fully differential inputs, a pipelined architecture, and digital error correction. This ADC is optimized for low-power, high-dynamic performance for medical imaging, munications, and instrumentation applications. The MAX1126 operates from a 1.7V to 1.9V single supply and consumes only 563m W while delivering a 69.9d B signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1126 Features an 813µA power-down mode for idle periods. An internal 1.24V precision bandgap reference sets the ADC’s full-scale range. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. A single-ended clock controls the conversion process. An internal duty-cycle equalizer allows for wide variations in input-clock duty cycle. An on-chip phaselocked loop (PLL) generates the high-speed serial low-voltage differential signaling (LVDS) clock. The MAX1126 provides serial LVDS outputs for data, clock, and frame alignment signals. The output data is presented in two’s plement or binary format. Refer to the MAX1127...