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MAX5865 - Ultra-Low-Power / High-Dynamic- Performance / 40Msps Analog Front End

Key Features

  • o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs o Ultra-Low Power 75.6mW at fCLK = 40MHz (Transceiver Mode) 64mW at fCLK = 22MHz (Transceiver Mode) Low-Current Idle and Shutdown Modes o Excellent Dynamic Performance 48.4dB SINAD at fIN = 5.5MHz (ADC) 70dB SFDR at fOUT = 2.2MHz (DAC) o Excellent Gain/Phase Match ±0.2° Phase, ±0.05dB Gain at fIN = 5.5MHz (ADC) o Internal/External Reference Option o +1.8V to +3.3V Digital Output Level (TTL/CMOS Compatible) o Multiplexed Parallel Digital Input/Out.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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19-2916; Rev 1; 10/03 KIT ATION EVALU E L B AVAILA Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End General Description Features o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs o Ultra-Low Power 75.6mW at fCLK = 40MHz (Transceiver Mode) 64mW at fCLK = 22MHz (Transceiver Mode) Low-Current Idle and Shutdown Modes o Excellent Dynamic Performance 48.4dB SINAD at fIN = 5.5MHz (ADC) 70dB SFDR at fOUT = 2.2MHz (DAC) o Excellent Gain/Phase Match ±0.2° Phase, ±0.05dB Gain at fIN = 5.5MHz (ADC) o Internal/External Reference Option o +1.8V to +3.