Datasheet4U Logo Datasheet4U.com

MAX6323 - uP Supervisory Circuits

General Description

The MAX6323/MAX6324 microprocessor (µP) supervisory circuits monitor power supplies and µP activity in digital systems.

A watchdog timer looks for activity outside an expected window of operation.

Six lasertrimmed reset thresholds are available with ±2.5% accuracy from +2.32V to +4.63V.

Key Features

  • MAX6323/MAX6324 Ordering Information PART.
  • TEMP RANGE.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MAX6320 5-Pin uP Supervisory Maxim Integrated
MAX6321 5-Pin uP Supervisory Maxim Integrated
MAX6322 5-Pin uP Supervisory Maxim Integrated
MAX6324 uP Supervisory Maxim Integrated
MAX6326 3-pin ultra-low power SC70/SOT microprocessor reset circuit NXP

Other Datasheets by Maxim Integrated (now Analog Devices)

Part Number Description
MAX632 CMOS Fixed/Adjustable Output Step-Up Switching Regulators
MAX6325 Voltage References
MAX6326 3-Pin / Ultra-Low-Power SC70/SOT uP Reset Circuits
MAX6327 3-Pin / Ultra-Low-Power SC70/SOT uP Reset Circuits
MAX6328 3-Pin / Ultra-Low-Power SC70/SOT uP Reset Circuits

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
19-1838; Rev 2; 2/03 µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset General Description The MAX6323/MAX6324 microprocessor (µP) supervisory circuits monitor power supplies and µP activity in digital systems. A watchdog timer looks for activity outside an expected window of operation. Six lasertrimmed reset thresholds are available with ±2.5% accuracy from +2.32V to +4.63V. Valid RESET output is guaranteed down to VCC = +1.2V. The RESET output is either push-pull (MAX6323) or open-drain (MAX6324). RESET is asserted low when VCC falls below the reset threshold, or when the manual reset input (MR) is asserted low. RESET remains asserted for at least 100ms after VCC rises above the reset threshold and MR is deasserted.