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MAX9160 - LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver

Description

The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks.

Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable.

The LVDS input has a fail-safe function.

Features

  • o LVDS or LVTTL/LVCMOS Input Selection o LVDS Input Fail-Safe Sets Outputs High for Open, Undriven Short, or Undriven Parallel Termination o Two Output Banks with Separate Bank Enables o Integrated Output Series Termination for 60Ω Lines o 200ps (max) Output-to-Output Skew o ±100ps (max) Peak-to-Peak Added Output Jitter o 42% to 58% Output Duty Cycle at 125MHz o Guaranteed 125MHz Operating Frequency o LVDS Input Is High Impedance with VCC = 0V or Open (Hot Swappable) o 28-Pin Exposed- and Nonexp.

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Datasheet preview – MAX9160

Datasheet Details

Part number MAX9160
Manufacturer Maxim
File Size 348.22 KB
Description LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
Datasheet download datasheet MAX9160 Datasheet
Additional preview pages of the MAX9160 datasheet.

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Full PDF Text Transcription

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19-2392; Rev 0; 4/02 LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver General Description The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The MAX9160 has a propagation delay that can be adjusted using an external resistor to set the bias current for an internal delay cell. The LVTTL/LVCMOS outputs feature 200ps maximum output-to-output skew and ±100ps maximum added peak-to-peak jitter. The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of -40°C to +85°C.
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