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MAX9160 Datasheet LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver

Manufacturer: Maxim Integrated (now Analog Devices)

General Description

The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks.

Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable.

The LVDS input has a fail-safe function.

Overview

19-2392; Rev 0; 4/02 LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock.

Key Features

  • o LVDS or LVTTL/LVCMOS Input Selection o LVDS Input Fail-Safe Sets Outputs High for Open, Undriven Short, or Undriven Parallel Termination o Two Output Banks with Separate Bank Enables o Integrated Output Series Termination for 60Ω Lines o 200ps (max) Output-to-Output Skew o ±100ps (max) Peak-to-Peak Added Output Jitter o 42% to 58% Output Duty Cycle at 125MHz o Guaranteed 125MHz Operating Frequency o LVDS Input Is High Impedance with VCC = 0V or Open (Hot Swappable) o 28-Pin Exposed- and Nonexp.