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MT2523 - Monolithic chip integrating leading edge power management unit

General Description

Initial draft Document format update Review completed Update power performance Update PMU AUXADC specifications Update BT specifications Update platform performance specification Update pin-mux description, power consumption data, peripheral functions by power scenario, and clock sources.

Key Features

  • Platform.
  • 208MHz ARM® Cortex®-M4 with FPU.
  • High power efficiency with system DVFS o 1.3V, 208MHz o 1.2V, 104MHz o 1.1V, 104MHz o 0.9V, 26MHz o 0.7V, 32kHz.
  • Hardware DVS from deep sleep (0.7V) to active (0.9V or above).
  • Fast 7µs wakeup from sleep to active.
  • Hardware DFS from 1.6MHz to 208MHz.
  • 17 DMA channels.
  • One RTC timer and six GPTs.
  • Crypto engine AES 128/192/256 bits.
  • True random number generator.
  • Ambien.

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Datasheet Details

Part number MT2523
Manufacturer MediaTek
File Size 3.19 MB
Description Monolithic chip integrating leading edge power management unit
Datasheet download datasheet MT2523 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MT2523 Series Datasheet Version: Release date: 1.4 13 January 2017 © 2015 - 2017 MediaTek Inc. This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s). MediaTek cannot grant you permission for any material that is owned by third parties. You may only use or reproduce this document if you have agreed to and been bound by the applicable license agreement with MediaTek (“License Agreement”) and been granted explicit permission within the License Agreement (“Permitted User”). If you are not a Permitted User, please cease any access or use of this document immediately. Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited. THIS DOCUMENT IS PROVIDED ON AN “AS-IS” BASIS ONLY.