MG82FG5A64 Overview
8051-Based MCU MG82FG5A64 Data Sheet Version: A2.4 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice.
MG82FG5A64 Key Features
- 1-T 80C51 Central Processing Unit
- AP Flash mapping (60KB, 0000h~EFFFh)
- IAP Flash mapping (2.5KB, F000h~F9FFh)
- ISP Flash mapping (1.5KB, FA00h~FFFFh), ISP Boot code
- Data RAM ━ On-chip 256 bytes scratch-pad RAM ━ 5120 bytes expanded RAM (XRAM)
- Dual data pointer
- Variable length MOVX for slow SRAM/Peripherals
- Interrupt controller ━ 16 sources, four-level-priority interrupt capability ━ Four external interrupt inputs, nINT0, nIN
- Programmable 16-bit counter/timer Array (PCA) with 6 pare/capture modules ━ Capture mode ━ 16-bit software timer mode ━
- Keypad Interrupt (P0/P2/P5/P6)