Z2V56S20BTP
DESCRIPTION
Z2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and Z2V56S30BTP is organized as 4-bank x 8,388,608-word x 8-bit and Z2V56S40BTP is organized as 4-bank x 4,194, 304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
FEATURES
Z2V56S20BTP, Z2V56S30BTP and Z2V56S40BTP achieve very high speed clock rates up to 166MHz, and are suitable for main memories or graphic memories in puter systems.
ITEM t CLK Clock Cycle Time
(Min.)
CL=2 CL=3
Z2V56S20/30/40BTP
-6 -7 -75 -8
- - 10 10
6 7 7.5
8 t RAS Active to Precharge mand Period (Min.)
42 45
45 48 t RCD Row to Column Delay t AC Access Time from CLK t RC Ref /Active mand Period
(Min.) (Max.) (Min.)
CL=2 CL=3
15 20 --
20 6
5 5.4
60 63 67.5
20 6 6 70
V56S20 100 100
Icc1 Operation Current (Single Bank)
(Max.)
V56S30 110 110
V56S40 130 130
Icc6 Self Refresh Current
- Single 3.3V ±0.3V power supply
(Max.)...
