MT41J128M16 Datasheet | Micon

2Gb: x4, x8, x16 DDR3 SDRAM Features DDR3 SDRAM MT41J512M4 - 64 Meg x 4 x 8 Banks MT41J256M8 - 32 Meg x 8 x 8 Banks MT41J128M16 - 16 Meg x 16 x 8 Banks Features - - - - - - - - - - - - - - VDD = V DDQ = 1.5V ±0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS READ latency (CL) Posted CAS additive latency (AL) Programmable CAS WRITE latency (CWL) based on tCK Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly...