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MDB1900ZC - Zero Delay Buffer

Description

The MDB1900ZC is a true zero delay buffer with a fully integrated, high-performance, low-power, and low-phase noise programmable PLL.

The MDB1900ZC is capable of distributing the reference clocks for PCIe (Gen1/Gen2/Gen3), SATA, ESI, SAS, SMI, and Intel® Quickpath Interconnect (QPI).

Features

  • Supports zero delay (0ps) buffer mode for 100MHz and 133MHz clock frequencies.
  • Internal feedback path for zero delay (PLL) mode.
  • Zero delay (PLL) mode can filter jitte.

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Datasheet preview – MDB1900ZC

Datasheet Details

Part number MDB1900ZC
Manufacturer Micrel Semiconductor
File Size 911.55 KB
Description Zero Delay Buffer
Datasheet download datasheet MDB1900ZC Datasheet
Additional preview pages of the MDB1900ZC datasheet.

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Full PDF Text Transcription

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MDB1900ZC Zero Delay Buffer for PCIe (Gen1/Gen2/Gen3), SAS, SATA, ESI, and QPI General Description The MDB1900ZC is a true zero delay buffer with a fully integrated, high-performance, low-power, and low-phase noise programmable PLL. The MDB1900ZC is capable of distributing the reference clocks for PCIe (Gen1/Gen2/Gen3), SATA, ESI, SAS, SMI, and Intel® Quickpath Interconnect (QPI). The MDB1900ZC works in conjunction with a CK410B+, CK509B, or CK420BQ clock synthesizer to provide reference clocks to multiple agents. The MDB1900ZC is designed for Intel’s DB1900Z specification with the exception that the zero delay buffer feedback path is inside the IC and does not need to be built onto the PCB. Datasheets and support documentation are available on Micrel’s website at: www.micrel.com.
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