SY100E137 Datasheet | Micrel Semiconductor

Micrel, Inc. 8-BIT RIPPLE COUNTER SY10E137 SY1S0YE10103E7137 Features s 1.8GHz min. count frequency s Extended 100E VEE range of - 4.2V to - 5.5V s Synchronous and asynchronous enable pins s Differential clock input and data output pins s VBB output for single-ended use s Asynchronous Master Reset s Internal 75KΩ input pull-down resistors s Available in 28-pin PLCC packge PIN NAMES Pin CLK, CLK Q0- Q7, Q0- Q7 A_Start EN1, EN2 MR VBB VCCO Function Differential Clock Inputs Differential Q Outputs Asynchronous Enable Input Synchronous Enable Inputs Asynchronous Master Reset Switching Reference Output VCC to Output DESCRIPTION The SY10/100E137 are very high speed binary ripple counters. The two least significant bits were designed with very fast edge rates, while the more significant bits maintain standard ECLin PS output edge rates. This allows the counters to operate at very high frequencies, while maintaining a moderate power dissipation level. The devices are ideally suited for multiple frequency clock generation, as well as for counters in highperformance ATE time measurement boards. Both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. The asynchronous enable input, A_Start, when asserted, enables the counter while overriding any synchronous enable signals. The E137 Features XOR'ed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted, the counter bees disabled on the next CLK transition. All outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted in order to re-enable the counter. Asserting both synchronous enables causes the counter to bee enabled on the next transition of the CLK. EN1 (or EN2) and CLK edges are coincident. Sufficient delay has been inserted in the CLK path (to pensate for the XOR gate delay and the internal D-flip-flop set-up time) to ensure that the...