SY100E175 Datasheet | Micrel Semiconductor

Micrel, Inc. 9-BIT LATCH WITH PARITY SY10E175 SY1S0YE10107E5175 Features s 9-bit latch s Extended 100E VEE range of - 4.2V to - 5.5V s Parity detection/generation s 800ps max. D to Output s Reset s Internal 75KΩ input pull-down resistors s Fully patible with Motorola MC10E/100E175 s Available in 28-pin PLCC package BLOCK DIAGRAM D0 D8 EN R bits 1- 7 Q0 EN R Q8 DESCRIPTION The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity) and using ODDPAR as the byte parity output. The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level. PIN NAMES Pin D0 - D8 LEN MR Q0 - Q8 ODDPAR VCCO Function Data Inputs Latch Enable Master Reset Data Outputs Parity Output VCC to Output ODDPAR LEN MR EN R M9999-032006 hbwhelp@micrel. or (408) 955-1690 Rev.: F Amendment: /0 Issue Date: March...