SY100E241 Datasheet | Micrel Semiconductor

Micrel, Inc. 8-BIT SCANNABLE REGISTER SY10E241 SY1S0YE10204E1241 SY100E241 Features s 1000ps max. CLK to output s Extended 100E VEE range of - 4.2V to - 5.5V s SHIFT overrides HOLD, /LOAD control s Asynchronous Master Reset s Pin-patible with E141 s Fully patible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully patible with Motorola MC10E/100E241 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E241 are 8-bit shiftable registers designed for use in new, high-performance ECL systems. Unlike the E141, the E241 Features internal data feedback organized such that the SHIFT control overrides the HOLD, /LOAD control. Thus, the normal operations of HOLD and LOAD can be toggled with a single control line without the need for external gating. This configuration also enables switching to scan mode with the single SHIFT control line. The eight inputs D0- D7 accept parallel input data, while S-IN accepts serial input data when in shift mode. Data is accepted a set-up time before the rising edge of CLK. Shifting is also acplished on the rising clock edge. A HIGH on the Master Reset pin (MR) asychronously resets all the registers to zero. BLOCK DIAGRAM S-IN D0 D1 - D6 BITS 1-6 DQ R DQ R Q0 Q1 - Q6 PIN NAMES Pin D0- D7 S-IN SEL0 SEL1 CLK MR Q0- Q7 VCCO Function Parallel Data Inputs Serial Data Input SHIFT Control HOLD, /LOAD Control Clock Master Reset Data Outputs VCC to Output D7 SEL1 (HOLD/LOAD) SEL0 (SHIFT) CLK MR DQ R Q7 M9999-032206 hbwhelp@micrel. or (408) 955-1690 Rev.: F Amendment: /0 Issue Date: December 2005 Micrel, Inc. SY10E241...