SY10E451 Description
The SY10/100E451 offer six D-type flip-flops with singleended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. A logic HIGH on the Master Reset (MR) input resets all outputs to a logic LOW.
SY10E451 Key Features
- Data Input + Clock Input
- Clock Input Data Outputs Master Reset Input VBB Output VCC to Output