Datasheet4U Logo Datasheet4U.com

SY10EP51V - Differential Clock D Flip-flop

Description

The SY10EP51V is a D flip-flop with reset and differential clock.

The device is pin and functionally equivalent to the EL51 device.

The reset input is an asynchronous, level triggered signal.

Features

  • s s s s s s 3.3V and 5V power supply options 320ps typical propagation delay Maximum frequency > 3GHz typical 75Ω internal input pulldown resistor Transistor count: 143 Available in 8-Pin (3mm) MSOP and SOIC packages ECL Pro™.

📥 Download Datasheet

Datasheet Details

Part number SY10EP51V
Manufacturer Micrel Semiconductor
File Size 108.42 KB
Description Differential Clock D Flip-flop
Datasheet download datasheet SY10EP51V Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SY10ELT23 DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR Synergy
SY10 SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT Raltron Electronics
SY100 3 Port Solenoid Valve Rubber Seal SMC
SY100EL11V 5V/3.3V ECL 1:2 Differential Fanout Buffe Microchip
SY100EL16S 5V VARIABLE OUTPUT SWING DIFFERENTIAL RECEIVER Synergy

Other Datasheets by Micrel Semiconductor

Part Number Description
SY10EP52V Differential Data And Clock D Flip-flop
SY10EP53V Differential Data And Clock D Flip-flop
SY10EP58V 2:1 Multiplexer
SY10EP01V 4-INPUT OR/NOR
SY10EP05V DIFFERENTIAL AND/NAND

Full PDF Text Transcription

Click to expand full text
Micrel 5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK ECL Pro™ SY10EP51V SY10EP51V FINAL ECL Pro™ FEATURES s s s s s s 3.3V and 5V power supply options 320ps typical propagation delay Maximum frequency > 3GHz typical 75Ω internal input pulldown resistor Transistor count: 143 Available in 8-Pin (3mm) MSOP and SOIC packages ECL Pro™ DESCRIPTION The SY10EP51V is a D flip-flop with reset and differential clock. The device is pin and functionally equivalent to the EL51 device. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when CLK is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK.
Published: |