SY10EP51V Datasheet | Micrel Semiconductor

Micrel 5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK ECL Pro™ SY10EP51V SY10EP51V FINAL ECL Pro™ Features s s s s s s 3.3V and 5V power supply options 320ps typical propagation delay Maximum frequency > 3GHz typical 75Ω internal input pulldown resistor Transistor count: 143 Available in 8-Pin (3mm) MSOP and SOIC packages ECL Pro™ DESCRIPTION The SY10EP51V is a D flip-flop with reset and differential clock. The device is pin and functionally equivalent to the EL51 device. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when CLK is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The differential clock inputs of the EP51V allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the /CLK input will be biased a VCC/2. PIN CONFIGURATION/BLOCK DIAGRAM RESET 1 D 2 CLK 3 /CLK 4 8 VCC 7 Q 6 /Q 5 VEE Flip Flop .. PIN NAMES Pin Function ECL Clock Inputs ECL Asynchronous Reset ECL Data Input ECL Data Outputs Positive Supply Negative, 0 Supply Available in 8-Pin SOIC and MSOP Packages CLK, /CLK RESET D Q, /Q VCC VEE TRUTH TABLE D L H X RESET L L H CLK Z Z X Q L H L Z = LOW to HIGH Transition ECL Pro is a trademark of Micrel, Inc. Rev.: C Amendment: /0 Issue Date: March 2003 Micrel ECL Pro™...