SY89218U
Overview
- Low-skew LVDS output banks with independently integrated clock divider and LVDS fanout buffer capable programmable ÷1, ÷2 and ÷4 divider options of handling clocks up to 1.5GHz. Optimized for
- Four output banks, 15 total outputs communications applications, the four independently
- Guaranteed AC performance over temperature and controlled output banks are phase-matched and can be voltage: configured for pass through (÷1), ÷2 or ÷4 divider ratios. - Accepts a clock frequency up to 1.5GHz The differential input includes Micrel’s unique, 3-pin - <1600ps IN-to-OUT propagation delay input termination architecture that allows the user to - <200ps rise/fall time interface to any differential signal (AC- or DC-coupled) - <35ps within bank skew as small as 100mV (200mVPP) without any level shifting
- Fail Safe Input or termination resistor networks in the signal path. The low-skew, low-jitter outputs are LVDS compatible with - Prevents outputs from oscillating extremely fast rise/fall times guaranteed to be less than
- Ultra-low jitter design: 200ps. - <1psRMS random jitter The /MR (master reset) input asynchronously resets the - <10psPP total jitter (clock) outputs. A four-clock delay after de-asserting /MR allows
- Patent-pending input termination and VT pin accepts the counters to synchronize and start the outputs from DC- and AC-coupled inputs (CML, PECL, LVDS) the same state without any runt pulse.
- LVDS-compatible outputs ® The SY89218U is part of Micrel’s Precision Edge
- CMOS/TTL-compatible output enable (EN) and product family. All support documentation can be found divider select control at Micrel's web site at: .
- 2.5V ±5% power supply
- -40°C to +85°C temperature range
