SY89858U Datasheet PDF (Precision Low Power 1:8 LVPECL Fanout Buffer)

SY89858U - Precision Low Power 1:8 LVPECL Fanout Buffer

Description

The SY89858U is a 2.5V/3.3V precision, highspeed, fully differential LVPECL 1:8 fanout buffer optimized to provide eight identical output copies with less than 30ps of skew and less than 10pspp total jitter.

It can process clock signals as fast as 2.0GHz.

Features

Precision Edge®.
Precision 1:8, LVPECL fanout buffer.
Low power: 238mW (2.5V).
Guaranteed AC performance over temperature and supply voltage:.
Wide operating frequency: DC to 2.0GHz.

Datasheet Details

Part number	SY89858U
Manufacturer	Micrel Semiconductor
File Size	422.95 KB
Description	Precision Low Power 1:8 LVPECL Fanout Buffer
Datasheet	SY89858U Datasheet
Additional preview pages of the SY89858U datasheet.

📁 Similar Datasheet

SY89874U - Programmable Clock Divider/Fanout Buffer (Microchip)

SY89206V - DIFFERENTIAL PECL/ECL RECEIVER/BUFFER (MICREL)

SY89216V - DIFFERENTIAL PECL/ECL RECEIVER/BUFFER (MICREL)

SY89230U - Clock Divider (Micrel)

SY89231U - Clock Divider (Micrel)

SY89297U - Precision CML Dual-Channel Programmable Delay (Microchip)

SY89306V - 3.3V/5V 2.5GHz Differential PECL/ECL Receiver/Buffer (Microchip)

SY8002A1 - 2A Synchronous Step Down Regulator (Silergy)

SY8002E1 - 2A Synchronous Step Down Regulator (Silergy)

SY8002I - 2A Synchronous Step Down Regulator (Silergy)

Full PDF Text Transcription

Click to expand full text

SY89858U Precision Low Power 1:8 LVPECL Fanout Buffer with Internal Termination General Description The SY89858U is a 2.5V/3.3V precision, highspeed, fully differential LVPECL 1:8 fanout buffer optimized to provide eight identical output copies with less than 30ps of skew and less than 10pspp total jitter. It can process clock signals as fast as 2.0GHz. The differential input includes Micrel’s unique, 3-pin input termination architecture that allows the SY89858U to directly interface to LVPECL, CML, and LVDS differential signals (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution.

Published: Sep 24, 2005 |