ANTC205 Datasheet | Micrel Semiconductor

Introduction The Jitter Blocker takes very noisy and jittery clocks and cleans out all the deterministic and excessive jitter. It can handle thousands of picoseconds of period jitter at its input and reduces that to below 100ps on the output. Eye-Opening Performance When Eyes Close Block Jitter Accumulation When Jitter Accumulates Block Deterministic Jitter Jitter Blocker Output Jitter Blocker Output When Deterministic Jitter Dominates Jitter Blocker Output Micrel Inc. - 2180 Fortune Drive - San Jose, CA 95131 - USA - tel +1 (408) 944-0800 - fax + 1 (408) 474-1000 - http://.micrel. September 16, 2014 Revision 1.0 Micrel, Inc. - Jitter Blocker Multi-purpose ICs, like FPGAs or multiple-output clock generators, can make a reference clock for your system, but generally this clock is very noisy. These ICs internally deal with a multitude of signals and cross-talk often creates significant deterministic jitter in the generated clock. The period jitter can be as bad as 300ps peak-topeak or greater. There are also systems, like IEEE1588, that can create a clock with very high frequency accuracy, but the clock is assembled from time slices and this causes very bad period jitter on the order of thousands of picoseconds. There are many applications that cannot handle this kind of period jitter and jitter attenuation is required to use that reference clock. However, when looking for jitter attenuating devices today, users often find only high-end devices with high-end price tags. There was nothing available to take that clock with 300ps or more (peak-topeak) of period jitter and clean it up by 50ps to 100ps, making it useful for many more applications and without the high-end price tag. Micrel’s Jitter Blocker was designed to fill that void, to be better suited for a wide variety of applications at a much more reasonable cost and with a very small form factor. The PL902 Jitter Blocker is able to take extremely jittery clocks, with up to thousands of...