DESCRIPTION
Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. BLOCK DIAGRAM SEL VCON Oscillator Amplifier XIN w/ integrated varicaps XOUT PLL (Phase Locked Loop) PLL by-pass OE Q Q PL520-00 DIE SPECIFICATIONS Name Value Size 65 x 62 mil Reverse side GND Pad dimensions 80 m icron x 80 micron Th ic kn e s s 10 mil 62 mil DIE CONFIGURATION 65 mil OUTSEL0^ VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 25 24 23 22 21 20 19 18 XIN 26 XOUT 27 Die ID: A1919-19A SEL3^ 28 SEL2^ 29 OE 30 CTRL VCON 31 C502A 12345 6 78 (1550,1475) 17 GNDBUF 16 CMOS 15 LVDSB 14 PECLB 13 VDDBUF 12 VDDBUF 11 PECL 10 LVDS 9 OE_SEL^ GND GND GND GND GND NC GND GNDBUF Y (0,0) X Note: ^ denotes internal pull up OUTPUT SELECTION AND ENABLE OUTSEL1 (Pad #18) 0 0 1 1 OUTSEL0 (Pad #25) 0 1 0 1 Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) OE_SELECT (Pad #9) 0 1 (Default) OE_CTRL (Pad #30) 0 1 (Default) 0 (Default) 1 State Tr i- s t a te Output enabled Output enabled Tr i- s t a te Pad #9, 18, 25: Bond to GND to set to “0”.
Micrel
