PL520-30 Datasheet PDF

Micrel PL520-30

The PL520-30 is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with selectable PECL or LVDS outputs and OE logic (enable high or enable low). Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability.

Part No.	PL520-30
Datasheet	PL520-30 Download
Manufacturer	Micrel
Description	PECL and LVDS Low Phase Noise VCXO
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DESCRIPTION

Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. BLOCK DIAGRAM VCON Oscillator Amplifier w/ XIN integrated varicaps XOUT OE Q Q PL520-30 62 mil DIE CONFIGURATION 65 mil OESEL^ VDD VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 XIN 26 XOUT 27 Die ID: A1313-13B N/C 28 N/C 29 OE 30 CTRL VCON 31 C502A 12345 6 78 (1550,1475) 17 GNDBUF 16 N/C 15 LVDSB 14 PECLB 13 VDDBUF 12 VDDBUF 11 PECL 10 LVDS 9 OUTSEL^ Y (0,0) X GND GND GND GND GND Reserved GNDBUF GNDBUF DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Th ic kn e s s Value 62 x 65 mil GND 80 m icron x 80 micron 10 mil OUTPUT SELECTION AND ENABLE OUTSEL (Pad #9) 0 1 Selected Output L VD S PECL (default) OESEL (Pad #25) 0 1 (default) OE_CTRL (Pad #30) 0 1 0 1 State Tr i- s t a te Output enabled (default) Output enabled (default) Tr i- s t a te Pad #9, #25: Bond to GND to set to “0”. Internal pull up. Pad #30: Logical states defined by PECL levels if OESEL is “1” Logical states defined by CMOS levels if OESEL is “0” Micrel Inc.