SPNZ801113 Datasheet | Micrel Semiconductor

Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces Rev 1.0 General Description The SPNZ801113 is a highly-integrated, Layer 2 managed 4-port switch with optimized design, plentiful Features and smallest package size. It is designed for cost-sensitive 10/100Mbps 4-port switch systems with on-chip termination, lowest-power consumption, and small package to save system cost. It has 1.4Gbps highperformance memory bandwidth, shared memory-based switch fabric with full non-blocking configuration. It also provides an extensive feature set such as the power management, programmable rate limiting and priority ratio, tag/port-based VLAN, packet filtering, quality of service (Qo S), four queue prioritization, management interface, MIB counters. Port 3 and Port 4 support either MII or RMII interfaces with SW3-MII/RMII and SW4-MII/RMII (see Functional Diagram) for SPNZ801113 uplink data interface. An industrial temperature-grade version of the SPNY80111 is also available (see “Ordering Information” section).The SPNZ801113 provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The SPNZ801113 consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technology, media access control (MAC) units, a high-speed nonblocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The SPNZ801113 contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of the PHYs can be accessed through the MDC/MDIO interface. EEPROM can set all control registers by I2C controller interface for the unmanaged mode. Datasheets and support documentation can be found on Micrel’s web site at: .micrel.. Functional Diagram Micrel Inc. - 2180 Fortune Drive - San Jose, CA 95131 - USA - tel +1 (408) 944-0800 - fax + 1 (408)...