FEATURES
s Up to 2ns delay range s Extended 100E VEE range of –4.2V to –5.5V s ≈20ps digital step resolution s Linear input for tighter resolution s >1GHz bandwidth s On-chip cascade circuitry s 75KkΩ input pulldown resistor s Fully compatible with Motorola MC10E/100E196 s Available in 28-pin PLCC package DESCRIPTION
These two elements provide the E196 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. The FTUNE input takes an analog coltage and applies it to an internal linear ramp for reducing the 20s resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.
Micrel
