Micrel SY100S351
The SY100S351 offers six D-type, edge-triggered, master/ slave flip-flops with differential outputs, and is designed for use in high-performance ECL systems. The flip-flops are controlled by the signal from the logical OR operation on a pair of common clock signals (CPa, CPb). The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW.| Part No. | SY100S351 |
|---|---|
| Datasheet | SY100S351 Download |
| Manufacturer |  Micrel |
| Description | Hex D Flip-flop |
| Buy | Stock & Price |
FEATURES
DESCRIPTION
● Max. toggle frequency of 700MHz● Clock to Q max. of 1200ps
● IEE min. of –98mA
● Industry standard 100K ECL levels
● Extended supply voltage option: VEE = –4.2V to –5.5V
● Voltage and temperature compensation for improved noise immunity
● Internal 75kΩ input pull-down resistors
● 50% faster than Fairchild 300K
● Better than 20% lower power than Fairchild
● Function and pinout compatible with Fairchild F100K
● Available in 28-pin PLCC package Data enters the master when both CPa and CPb are LOW and transfers to the slave when either CPa or CPb (or both) go to a logic HIGH. The inputs on this device have 75kΩ pull-down resistors. BLOCK DIAGRAM PIN NAMES Pin D0 — D5 CPa, CPb MR Q0 — Q5 Q0 — Q5 VEES VCCA Function Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs M9999-060910 hbwhelp@micrel.com or (408) 955-1690 1 Rev.: I Amendment: /0 Issue Date: June 2010 Micrel, Inc. SY100S351...
