GENERAL DESCRIPTION
The output stage is a high speed comparator circuit with both TTL and ECL outputs. An enable pin is included for added control. The Link Detect circuit provides a Link Monitor function with a user selectable reference voltage. This circuit monitors the peaks of the input signal and provides a logic level output indicating when the input falls below an acceptable level. This output can be used to disable the quantizer and/or drive an LED, providing a visible link status. FEATURES
Data rates up to 40MHz or 80MBd Can be powered by either +5V providing TTL or raised ECL level outputs or –5.2V providing ECL levels s Low noise design: 25µV RMS over bandwidth s Adjustable Link Monitor function with hystersis s Wide 55dB input dynamic range s Low power design s ML4624 is pin compatible with the ML4621 s s APPLICATIONS
s s s IEEE 802.3 10BASE-FL Receiver IEEE 802.5 fiber optic token ring, 4 and 16mbps Fiber Optic Data Communications and Telecommunications Receivers ML4622/ML...