ATSAMR30M18A Datasheet | Microchip Technology

overview of necessary sections of the module. For a detailed description of each peripheral, refer to the ATSAMR30E18A datasheet. Features - Processor - ARM® Cortex®-M0+ CPU running at up to 48 MHz - Single-cycle hardware multiplier - Micro Trace Buffer (MTB) - Memories - 256 KB in-system self-programmable Flash - 32 KB SRAM - 8 KB low-power RAM - System - Power-on Reset (POR) and Brown-out Detection (BOD) - Internal clock option with 48 MHz Digital Frequency Locked Loop (DFLL48M) and 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M) - External Interrupt Controller (EIC) - Up to 14 external interrupts - One non-maskable interrupt - Two-pin Serial Wire Debug (SWD) programming, test and debugging interface - Low Power - Idle and Standby Sleep modes - Sleep walking peripherals - Integrated Ultra-Low Power Transceiver for 700/800/900 MHz ISM Band: - Chinese WPAN band from 779 to 787 MHz - European SRD band from 863 to 870 MHz - North American ISM band from 902 to 928 MHz © 2018 Microchip Technology Inc. DS70005384A-page 1 - Japanese band from 915 to 930 MHz - Direct Sequence Spread Spectrum with Different Modulation and Data Rates: - BPSK with 20 and 40 kb/s, pliant to IEEE 802.15.4-2003/2006/2011 - O-QPSK with 100 and 250kb/s, pliant to IEEE 802.15.4-2006/2011 - O-QPSK with 200, 400, 500, and 1000kb/s PSDU data rate - Industry-leading link budget: - RX sensitivity up to -105 d Bm - TX output power up to +8.7 d Bm - Hardware-assisted MAC: - Auto-Acknowledge - Auto-Retry - CSMA-CA and Listen Before Talk (LBT) - Automatic address filtering and automated FCS check - Special 802.15.4-2011 hardware...