KSZ8091MNX - 10BASE-T/100BASE-TX Physical Layer Transceiver

Description

and Configuration 5 3.0 Functional Description 15 4.0 Register Descriptions 40 5.0 Operational Characteristics 57 6.0 Electrical Characteristics 58 7.0 Timing Diagrams

Features

Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver.
MII Interface Support (KSZ8091MNX).
RMII v1.2 interface support with a 50 MHz reference clock output to MAC, and an option to input a 50 MHz reference clock (KSZ8091RNB).
Back-to-Back Mode Support for a 100 Mbps Copper Repeater.
MDC/MDIO Management Interface for PHY Register Configuration.
Programmable Interrupt Output.
LED Outputs for Link and Activity Statu.

Microchip

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Datasheet Details

Part number	KSZ8091MNX
Manufacturer	Microchip
File Size	2.44 MB
Description	10BASE-T/100BASE-TX Physical Layer Transceiver
Datasheet	KSZ8091MNX Datasheet
Additional preview pages of the KSZ8091MNX datasheet.

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Full PDF Text Transcription

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KSZ8091MNX/RNB 10BASE-T/100BASE-TX Physical Layer Transceiver Features • Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver • MII Interface Support (KSZ8091MNX) • RMII v1.

Published: Feb 8, 2017 |