KSZ8895FQX Datasheet | Microchip Technology

Features Advanced Switch Features - IEEE 802.1q VLAN Support for up to 128 Active VLAN Groups (Full-Range 4096 of VLAN IDs) - Static MAC Table Supports up to 32 Entries - VLAN ID Tag/Untagged Options, Per Port Basis - IEEE 802.1p/q Tag Insertion or Removal on a Per Port Basis Based on Ingress Port (Egress) - Programmable Rate Limiting at the Ingress and Egress on a Per Port Basis - Jitter-Free Per Packet Based Rate Limiting Support - Broadcast Storm Protection with Percentage Control (Global and Per Port Basis) - IEEE 802.1d Rapid Spanning Tree Protocol RSTP Support - Tail Tag Mode (1 Byte Added Before FCS) Support at Port 5 to Inform the Processor Which Ingress Port Receives the Packet - 1.4 Gbps High-Performance Memory Bandwidth and Shared Memory Based Switch Fabric with Fully Non-Blocking Configuration - Dual MII with MAC 5 and PHY 5 on Port 5, SW5MII/RMII for MAC 5 and P5-MII/RMII for PHY 5 - Enable/Disable Option for Huge Frame Size up to 2000 Bytes Per Frame - IGMP v1/v2 Snooping (IPv4) Support for Multicast Packet Filtering - IPv4/IPv6 Qo S Support - Support Unknown Unicast/Multicast Address and Unknown VID Packet Filtering - Self-Address Filtering prehensive Configuration Register Access - Serial Management Interface (MDC/MDIO) to All PHYs Registers and SMI Interface (MDC/MDIO) to All Registers - High-Speed SPI (up to 25 MHz) and I2C Master Interface to all Internal Registers - I/O Pins Strapping and EEPROM to Program Selective Registers in Unmanaged Switch Mode - Control Registers Configurable on the Fly (Port Priority, 802.1p/d/q, AN…) Qo S/Co S Packet Prioritization Support - Per Port, 802.1p and Diff Serv-Based - 1/2/4-Queue Qo S Prioritization Selection - Programmable Weighted Fair Queuing for Ratio Control - Re-Mapping of 802.1p Priority Field Per Port Basis Integrated 5-Port 10/100 Ethernet Switch - New Generation Switch with Five MACs and Five PHYs that are Fully pliant with the IEEE 802.3u Standard - PHYs Designed with Patented Enhanced Mixed Signal...