PIC32MZ1024EFG100 Datasheet | Microchip Technology

Features - 2.1V to 3.6V, -40ºC to +85ºC, DC to 252 MHz - 2.1V to 3.6V, -40ºC to +125ºC, DC to 180 MHz Core: 252 MHz (up to 415 DMIPS) M-Class - 16 KB I-Cache, 4 KB D-Cache - FPU for 32-bit and 64-bit floating point math - MMU for optimum embedded OS execution - micro MIPS™ mode for up to 35% smaller code size - DSP-enhanced core: - Four 64-bit accumulators - Single-cycle MAC, saturating, and fractional math - IEEE 754-pliant - Code-efficient (C and Assembly) architecture Clock Management - Programmable PLLs and oscillator clock sources - Fail-Safe Clock Monitor (FSCM) - Independent Watchdog Timers (WDT) and Deadman Timer (DMT) - Fast wake-up and start-up Power Management - Low-power modes (Sleep and Idle) - Integrated Power-on Reset (POR) and Brown-out Reset (BOR) Memory Interfaces - 50 MHz External Bus Interface (EBI) - 50 MHz Serial Quad Interface (SQI) Audio and Graphics Interfaces - Graphics interfaces: EBI or PMP - Audio data munication: I2S, LJ, and RJ - Audio control interfaces: SPI and I2C - Audio master clock: Fractional clock frequencies with USB synchronization High-Speed (HS) munication Interfaces  (with Dedicated DMA) - USB 2.0 Hi-Speed On-The-Go (OTG) controller - 10/100 Mbps Ethernet MAC with MII and RMII interface Security Features - Crypto Engine with RNG for data encryption/decryption and authentication (AES, 3DES, SHA, MD5, and HMAC) - Advanced memory protection: - Peripheral and memory region access control - 12-bit ADC module: - 18 Msps with up to six Sample and Hold (S&H) circuits (five dedicated and one...