SAMA5D21
Features
- Arm Cortex-A5 Core
- Armv7-A architecture
- Arm Trust Zone
- NEON™ Media Processing Engine
- Up to 500 MHz
- ETM/ETB 8 Kbytes
- Memory Architecture
- Memory Management Unit (MMU)
- 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
- 128-Kbyte L2 cache configurable to be used as an internal SRAM
- One 128-Kbyte scrambled internal SRAM
- One 160-Kbyte internal ROM
- 64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader
- 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
- High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting up to 512 Mbytes 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off only) / LPDDR1/ LPDDR2/LPDDR3, including “on-the-fly” encryption/decryption path
- 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
- System Running up to 166 MHz in Typical Conditions
- Reset Controller (RSTC), Shutdown Controller (SHDWC), Periodic Interval Timer...
