SY100EL29V Datasheet | Microchip Technology

5V/3.3V Dual Differential Data and Clock D Flip-Flop with Set and Reset Features - 3.3V and 5V Power Supply Option - Differential D, CLK and Q - Extended VEE Range of - 3.0V to - 5.5V - VBB Output for Single-Ended Use - 1100 MHz Min. Toggle Frequency - Asynchronous Reset and Set - Available in 20-Pin SOIC Package Package Type SY100EL29V 20-Lead SOIC (Z) R0 VCC Q0 /Q0 S0 S1 VCC Q1 /Q1 VEE 20 19 18 17 16 15 14 13 12 11 D CLK D CLK 1 2 3 4 5 6 7 8 9 10 D0 /D0 CLK0 /CLK0 VBB D1 /D1 CLK1 /CLK1 R1 General Description The SY100EL29V is a dual differential register with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Reset (Rx) asynchronously resets the appropriate register so that the Q outputs go LOW. A HIGH on the Set (Sx) asynchronously resets the appropriate register so that the Q outputs go HIGH. The Set and Reset inputs cannot both be HIGH simultaneously. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the devices. The clamping action will assert the /D and the /CLK sides of the inputs. The non-inverting input will pull down to VEE and the inverting input will be biased around VCC/2. Because of the edge-triggered flip-flop nature of the devices, simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. The fully differential design of the devices makes them ideal for very high frequency applications where a registered data path is necessary.  2019 Microchip Technology Inc. DS20006241A-page 1 1.0 ELECTRICAL CHARACTERISTICS...