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SY100EL52 - 5V ECL Differential Data and Clock D Flip-Flop

General Description

The SY100EL52 is a differential data, differential clock D flip-flop.

Data enters the master portion of the flip-flop when the clock is low and is transferred to the slave, then the outputs, upon a positive transition of the clock.

Key Features

  • 365 ps Propagation Delay (typical).
  • 2.8 GHz Toggle Frequency (typical).
  • Internal 75 kΩ Input Pull-Down Resistors.
  • Available in 8-Lead SOIC Package General.

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SY100EL52 5V ECL Differential Data and Clock D Flip-Flop Features • 365 ps Propagation Delay (typical) • 2.8 GHz Toggle Frequency (typical) • Internal 75 kΩ Input Pull-Down Resistors • Available in 8-Lead SOIC Package General Description The SY100EL52 is a differential data, differential clock D flip-flop. Data enters the master portion of the flip-flop when the clock is low and is transferred to the slave, then the outputs, upon a positive transition of the clock. The differential clock inputs also allow the EL52 to be used as a negative edge triggered device. The EL52 employs input clamping circuitry so that, under open input conditions (pulled down to VEE), the outputs of the device will remain stable.