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TP2502 - P-Channel Vertical DMOS FET

General Description

The TP2502 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process.

Key Features

  • 2.4V Maximum Low Threshold.
  • High Input Impedance.
  • 125 pF Maximum Low Input Capacitance.
  • Fast Switching Speeds.
  • Low On-Resistance.
  • Free from Secondary Breakdown.
  • Low Input and Output Leakage.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TP2502 P-Channel Enhancement-Mode Vertical DMOS FET Features • –2.4V Maximum Low Threshold • High Input Impedance • 125 pF Maximum Low Input Capacitance • Fast Switching Speeds • Low On-Resistance • Free from Secondary Breakdown • Low Input and Output Leakage Applications • Logic-Level Interfaces (Ideal for TTL and CMOS) • Solid-State Relays • Battery-Operated Systems • Photovoltaic Drives • Analog Switches • General Purpose Line Drivers • Telecommunication Switches General Description The TP2502 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process.