TP5322 Datasheet | Microchip Technology

Features - - 2.4V Maximum Low Threshold - High Input Impedance - 110 p F Maximum Low Input Capacitance - Fast Switching Speeds - Low On-Resistance - Free from Secondary Breakdown - Low Input and Output Leakage Applications - Logic-Level Interfaces (Ideal for TTL and CMOS) - Battery-Operated Systems - Photovoltaic Drives - Analog Switches - General Purpose Line Drivers - Telemunication Switches General Description The TP5322 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process. This bination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Microchip’s vertical DMOS FETs are ideally suited for a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Package Types 3-lead SOT-23 (Top view) DRAIN SOURCE GATE See Table 2-1 and Table 2-2 for pin information. 3-lead SOT-89 (Top view) DRAIN SOURCE DRAIN GATE  2020 Microchip Technology Inc. DS20005973A-page 1 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum...