ZL30250
Overview
- One Crystal/CMOS Input
- Two Differential/CMOS Inputs
- One Single-Ended/CMOS Input
- Any Input Frequency from 9.72 MHz to 1250 MHz (9.72 MHz to 300 MHz for CMOS)
- Clock Selection by Pin or Register Control Low-Jitter Fractional-N APLL and 3 Outputs
- Any Output Frequency from <1 Hz to 1035 MHz
- High-Resolution Fractional Frequency Conver- sion with 0 ppm Error
- Easy-to-Configure, Encapsulated Design Requires No External VCXO or Loop Filter Components
- Each Output has Independent Dividers
- Output Jitter as Low as 0.16 ps RMS (12 kHz to 20 MHz Integration Band)
