dsPIC33CH512MP205
Key Features
- Four ADC Modules: - One module for Main core - Three modules for Secondary core - 12-bit, 3.25 Msps ADC - Up to 18 conversion channels - 250 ns conversion latency
- Four DAC/Analog Comparator Modules: - One module for Main core - Three modules for Secondary core - 12-bit DACs with hardware slope compensation - 15 ns analog comparators
- Three PGA Modules: - Three modules for Secondary core - Can be read by Main ADC
- Shared DAC/Analog Output: - DAC/analog comparator outputs - PGA outputs Communication Interfaces
- Three UART Modules: - Two modules for Main core - One module for Secondary core - Support for DMX, LIN/J2602 protocols
- Three 4-Wire SPI/I2S Modules: - Two modules for Main core - One module for Secondary core
- Two CAN Flexible Data-Rate (FD) Modules for the Main Core
- Three I2C Modules: - Two modules for Main - One module for Secondary - Support for SMBus
- PPS to Allow Function Remap
- Programmable Cyclic Redundancy Check (CRC) for the Main
