dsPIC33CK128MC105 Overview
16-Bit dsPIC33CK CPU 128-256 Kbytes of Program Flash with ECC and 16-32K Data RAM Fast 6-Cycle Divide Code Efficient (C and Assembly) Architecture 40-Bit Wide Accumulators Single-Cycle (MAC/MPY) with Dual Data Fetch Single-Cycle, Mixed-Sign MUL Plus Hardware Divide 32-Bit Multiply Support Five Sets of Interrupt Context Selected Registers for Fast Interrupt Response Zero Overhead Looping RAM Memory Built-In Self-Test...
dsPIC33CK128MC105 Key Features
- High-Speed ADC module
- 12-bit with one shared SAR ADC core
- Configurable resolution (up to 12-bit)
- Up to 3.5 Msps conversion rate per channel at 12-bit resolution
- Up to 20 input channels
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Four digital parators
- Four oversampling filters for increased resolution
- Two Analog parators