dsPIC33CK512MP306 Datasheet | Microchip Technology

dsPIC33CK512MP608 Family 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data-Rate (CAN FD) Operating Conditions - 3V to 3.6V, -40°C to +125°C - DC to 100 MIPS - 3V to 3.6V, -40°C to +150°C: - DC to 70 MIPS Core: 16-Bit dsPIC33CK CPU - 256-512 Kbytes of Program Flash with ECC and 64 Kbytes of Data RAM - Fast Six-Cycle Divide - Flash with Dual Partition for LiveUpdate Capabilities - LiveUpdate - Code-Efficient (C and Assembly) Architecture - 40-Bit Wide Accumulators - Single-Cycle (MAC/MPY) with Dual Data Fetch - Single-Cycle, Mixed-Sign MUL Plus Hardware Divide - 32-Bit Multiply Support - Five Sets of Interrupt Context Selected Registers for Fast Interrupt Response - Zero Overhead Looping - RAM Memory Built-In Self-Test (MBIST) Clock Management - Fast RC (FRC) - Internal Oscillator - Programmable PLLs and Oscillator Clock Sources - Reference Clock Output - Fail-Safe Clock Monitor (FSCM) - Fast Wake-up and Start-up - 8 MHz Backup FRC (BFRC) with a Divider (244 decimal) to provide a Nominal 32.768 kHz Output with a 50% Duty Cycle Power Management...