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dsPIC33EP32GS502 Datasheet 16-bit Digital Signal Controllers

Manufacturer: Microchip Technology

Overview: dsPIC33EPXXGS50X FAMILY 16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators Operating Conditions • 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS Flash Architecture • Dual Partition Flash Program Memory with Live Update (64-Kbyte devices): - Supports programming while operating - Supports partition soft swap Core: 16-Bit dsPIC33E CPU • Code-Efficient (C and Assembly) Architecture • Two 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle Mixed-Sign MUL Plus Hardware Divide • 32-Bit Multiply Support • Two Additional Working Register Sets (reduces context switching) Clock Management • ±0.9% Internal Oscillator • Programmable PLLs and Oscillator Clock Sources • Fail-Safe Clock Monitor (FSCM) • Independent Watchdog Timer (WDT) • Fast Wake-up and Start-up Power Management • Low-Power Management modes (Sleep, Idle, Doze) • Integrated Power-on Reset and Brown-out Reset • 0.5 mA/MHz Dynamic Current (typical) • 10 μA IPD Current (typical) High-Speed PWM • Five PWM Generators (two outputs per generator) • Individual Time Base and Duty Cycle for each PWM • 1.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • High-Speed ADC module: - 12-bit with 4 dedicated SAR ADC cores and one shared SAR ADC core - Configurable resolution (up to 12-bit) for each ADC core - Up to 3.25 Msps conversion rate per channel at 12-bit resolution - 12 to 22 single-ended inputs - Dedicated result buffer for each analog channel - Flexible and independent ADC trigger sources - Two digital comparators - Two oversampling filters for increased resolution.
  • Four Rail-to-Rail Comparators with Hysteresis: - Dedicate.

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