24FC65-P
Description
The Microchip Technology Inc.
Key Features
- 1 MHz SE2.bus two wire protocol
- Up to eight devices may be connected to the same bus for up to 512K bits total memory
- Programmable block security options
- Programmable endurance options
- Schmitt trigger inputs for noise suppression
- Self-timed ERASE and WRITE cycles
- Power on/off data protection circuitry
- Endurance: - 10,000,000 E/W cycles guaranteed for a 4K block - 1,000,000 E/W cycles guaranteed for a 60K block
- Variable page size up to 64 bytes
- 8 byte x 8 line input cache (64 bytes) for fast write loads
