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MT8VDDT3264A - (MT8VDDTxx64A) 184-Pin DDR Sdram Dimms

Download the MT8VDDT3264A datasheet PDF. This datasheet also covers the MT8VDDT6464A variant, as both devices belong to the same (mt8vddtxx64a) 184-pin ddr sdram dimms family and are provided as variant models within a single manufacturer datasheet.

General Description

SYMBOL WE#, CAS#, RAS# CK0, CK0#, CK1, CK1#, CK2, CK2# TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.

Clock: CK, CK# are differential clock inputs.

Key Features

  • 184-pin dual in-line memory module (DIMM).
  • Fast data transfer rates: PC2100 or PC2700.
  • Utilizes 266 MT/s and 333 MT/s DDR SDRAM www. DataSheet4U. com components.
  • 128MB (16 Meg x 64), 256MB (32 Meg x 64), and 512MB (64 Meg x 64).
  • VDD = VDDQ = +2.5V.
  • VDDSPD = +2.3V to +3.6V.
  • 2.5V I/O (SSTL_2 compatible).
  • Commands entered on each positive CK edge.
  • DQS edge-aligned with data for READs; centeraligned with data for WRITEs.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MT8VDDT6464A_MicronSemiconductorProducts.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number MT8VDDT3264A
Manufacturer Micron Semiconductor Products
File Size 721.25 KB
Description (MT8VDDTxx64A) 184-Pin DDR Sdram Dimms
Datasheet download datasheet MT8VDDT3264A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM DDR SDRAM UNBUFFERED DIMM Features • 184-pin dual in-line memory module (DIMM) • Fast data transfer rates: PC2100 or PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM www.DataSheet4U.com components • 128MB (16 Meg x 64), 256MB (32 Meg x 64), and 512MB (64 Meg x 64) • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O (SSTL_2 compatible) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Bidirectional data strobe (DQS) transmitted/ received with data—i.e.