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46V16M16 - MT46V16M16

Description

BALL / PIN NUMBERS FBGA TSOP G2, G3 45, 46 SYMBOL CK, CK# TYPE Input DESCRIPTION Clock: CK and CK# are differential clock inputs.

All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#.

Features

  • 167 MHz Clock, 333 Mb/s/p data rate.
  • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V.
  • Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data capture (x16 has two - one per byte).
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle.
  • Differential clock inputs (CK and CK#).
  • Commands entered on each positive CK edge.
  • DQS edge-aligned with data for READs; centeraligned.

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Full PDF Text Transcription

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PRELIMINARY‡ 256Mb: x4, x8, x16 DDR333 SDRAM Addendum DOUBLE DATA RATE (DDR) SDRAM FEATURES • 167 MHz Clock, 333 Mb/s/p data rate • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • Bidirectional data strobe (DQS) transmitted/ received with data, i.e.
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