EDB5432BEPA Overview
1066 20 Mb/s/pin) Four-bit prefetch DDR architecture Four internal banks for concurrent operation Multiplexed, double data rate, mand/address inputs; mands entered on every CK edge Bidirectional/differential data strobe per byte of data (DQS/DQS#) Programmable READ and WRITE latencies (RL/WL) Programmable burst lengths: 4, 8, or 16 On-chip temperature sensor to control self refresh rate Partial-array self refresh...
EDB5432BEPA Key Features
- Ultra low-voltage core and I/O power supplies
- VDD2 = 1.14-1.30V
- VDDCA/VDDQ = 1.14-1.30V
- VDD1 = 1.70-1.95V
- Clock frequency range
- 533-10 MHz (data rate range: 1066-20 Mb/s/pin)
- Four-bit prefetch DDR architecture
- Four internal banks for concurrent operation
- Multiplexed, double data rate, mand/address
- Programmable READ and WRITE latencies (RL/WL)