Description
The MT28C3224P20 and MT28C3224P18 combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium.
Features
- Flexible dual-bank architecture.
- Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa.
- Organization: 2,048K x 16 (Flash) 256K x 16 (SRAM).
- Basic configuration: Flash Bank a (8Mb Flash for data storage).
- Eight 4K-word parameter blocks.
- Fifteen 32K-word blocks Bank b (24Mb Flash for program storage).
- Forty-eight 32K-word main blocks SRAM.
MT28C3224P18 Datasheet
