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MT28C6428P20 - FLASH AND SRAM COMBO MEMORY

Download the MT28C6428P20 datasheet PDF. This datasheet also covers the MT28C6428P18 variant, as both devices belong to the same flash and sram combo memory family and are provided as variant models within a single manufacturer datasheet.

General Description

The MT28C6428P20 and MT28C6428P18 combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium.

Key Features

  • Flexible dual-bank architecture.
  • Support for true concurrent operations with no latency: www. DataSheet4U. com Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa.
  • Organization: 4,096K x 16 (Flash) 512K x 16 (SRAM).
  • Basic configuration: Flash Bank a (16Mb Flash for data storage).
  • Eight 4K-word parameter blocks.
  • Thirty-one 32K-word blocks Bank b (48Mb Flash for program storage).
  • Ninety-six 32.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MT28C6428P18_MicronTechnology.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Micron Technology

Part Number Description
MT28C6428P18 FLASH AND SRAM COMBO MEMORY
MT28C128532W18 128Mb Multibank Burst Flash 32Mb ASYNC/PAGE CellularRAM COMBO Memory
MT28C128532W30D 128Mb Multibank Burst Flash 32Mb ASYNC/PAGE CellularRAM COMBO Memory
MT28C128564W18 128Mb Multibank Burst Flash 32Mb ASYNC/PAGE CellularRAM COMBO Memory
MT28C128564W30D 128Mb Multibank Burst Flash 32Mb ASYNC/PAGE CellularRAM COMBO Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ADVANCE‡ 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH AND SRAM COMBO MEMORY FEATURES • Flexible dual-bank architecture • Support for true concurrent operations with no latency: www.DataSheet4U.com Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa • Organization: 4,096K x 16 (Flash) 512K x 16 (SRAM) • Basic configuration: Flash Bank a (16Mb Flash for data storage) – Eight 4K-word parameter blocks – Thirty-one 32K-word blocks Bank b (48Mb Flash for program storage) – Ninety-six 32K-word main blocks SRAM 8Mb SRAM for data storage – 512K-words • F_VCC, VCCQ, F_VPP, S_VCC voltages MT28C6428P20 1.80V (MIN)/2.20V (MAX) F_VCC read voltage 1.80V (MIN)/2.20V (MAX) S_VCC read voltage 1.80V (MIN)/2.20V (MAX) VCCQ MT28C6428P18 1.