MT42L192M32D3 Datasheet | Micron Technology

Features Mobile LPDDR2 SDRAM MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features - Ultra low-voltage core and I/O power supplies - VDD2 = 1.14- 1.30V - VDDCA/VDDQ = 1.14- 1.30V - VDD1 = 1.70- 1.95V - Clock frequency range - 533- 10 MHz (data rate range: 1066- 20 Mb/s/pin) - Four-bit prefetch DDR architecture - Eight internal banks for concurrent operation - Multiplexed, double data rate, mand/address inputs; mands entered on every CK edge - Bidirectional/differential data strobe per byte of data (DQS/DQS#) - Programmable READ and WRITE latencies (RL/WL) - Programmable burst lengths: 4, 8, or 16 - Per-bank refresh for concurrent operation - On-chip temperature sensor to control self refresh rate - Partial-array self refresh (PASR) - Deep power-down mode (DPD) - Selectable output drive strength (DS) - Clock stop capability - Ro HS-pliant, “green” packaging Table 1: Key Timing Parameters Speed Grade -182 -25 -3 Clock Rate (MHz) 533 400 333 Data Rate (Mb/s/pin) RL WL 1066 800 667 8 6 5 4 3 2 Options - VDD2: 1.2V - Configuration - 16 Meg x 16 x 8 banks x 1 die - 8 Meg x 32 x 8 banks x 1 die - 8 Meg x 32 x 8 banks x 2 die - 16 Meg x 16 x 8 banks x 4 die - 8 Meg x 32 x 8 banks x 2 die - 8 Meg x 32 x 8 banks x 3 die - 8 Meg x 32 x 8 banks x 4 die - 16 Meg x 16 x 8 banks x 2 die + 8 Meg x 32 x 8 banks x 1 die - Device type - LPDDR2-S4, 1 die in package - LPDDR2-S4, 2 die in package - LPDDR2-S4, 3 die in package - LPDDR2-S4, 4 die in package - FBGA“green”...