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MT46H16M32LG - Mobile Low-Power DDR SDRAM

Download the MT46H16M32LG datasheet PDF. This datasheet also covers the MT46H32M16LF variant, as both devices belong to the same mobile low-power ddr sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

8 Functional Block Diagrams 9 Ball Assignments 11 Ball Descriptions 13 Package Dimensions 15 Electrical Specifications 17 Electrical Specifications IDD Parameters 20 Electrical Specifications AC Operating Conditions 26 Output Drive Characteristics 31 Functional Descripti

Key Features

  • Mobile Low-Power DDR SDRAM MT46H32M16LF.
  • 8 Meg x 16 x 4 banks MT46H16M32LF.
  • 4 Meg x 32 x 4 banks MT46H16M32LG.
  • 4 Meg x 32 x 4 banks Features.
  • VDD/VDDQ = 1.70.
  • 1.95V.
  • Bidirectional data strobe per byte of data (DQS).
  • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle.
  • Differential clock inputs (CK and CK#).
  • Commands entered on each positive CK edge.
  • DQS edge-aligned wit.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MT46H32M16LF-MicronTechnology.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Micron Technology

Part Number Description
MT46H16M32LF Mobile Low-Power DDR SDRAM
MT46H16M16LF Mobile Low-Power DDR SDRAM
MT46H128M16LF Mobile Low-Power DDR SDRAM
MT46H128M32L2 Mobile Low-Power DDR SDRAM
MT46H256M32L4 Mobile Low-Power DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
512Mb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H32M16LF – 8 Meg x 16 x 4 banks MT46H16M32LF – 4 Meg x 32 x 4 banks MT46H16M32LG – 4 Meg x 32 x 4 banks Features • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • 4 internal banks for concurrent operation • Data masks (DM) for masking write data; one mask per byte • Programmable burst lengths (BL): 2, 4, 8, or 16 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.