MT46H256M32L4
Key Features
- Mobile Low-Power DDR SDRAM
- VDD/VDDQ = 1.70–1.95V
- Bidirectional data strobe per byte of data (DQS)
- Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
- Differential clock inputs (CK and CK#)
- mands entered on each positive CK edge
- DQS edge-aligned with data for READs; centeraligned with data for WRITEs
- 4 internal banks for concurrent operation
- Data masks (DM) for masking write data; one mask per byte
- Concurrent auto precharge option is supported
