MT46V128M8 Description
Table 3: Speed Grade patibility Marking -5B -6T -75 -5B -6T -75 -75 PC3200 (3-3-3) Yes PC2700 (2.5-3-3).
MT46V128M8 Key Features
- 32 Meg x 8 x 4 banks MT46V128M8 a MT46V64M16 at
- 16 Meg x 16 x 4 banks .D w w Features Options Marking w
- Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two
- one per byte)
- Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
- Differential clock inputs (CK and CK#)
- mands entered on each positive CK edge
- DQS edge-aligned with data for READs; centeraligned with data for WRITEs
- DLL to align DQ and DQS transitions with CK
- Four internal banks for concurrent operation